4. Cache Organization and Coherency
4.2 Primary Data Cache
The processor has an on-chip 32-Kbyte primary data cache (also referred to simply as the data cache), which is a subset of the secondary cache. The data cache uses a fixed block size of 8 words and is two-way set associative (that is, two cache blocks are assigned to each set, as shown in Figure 4-3) with an LRU replacement algorithm.*1
Figure 4-3 Organization of Primary Data Cache
The data cache uses a write back protocol, which means a cache store writes data into the cache instead of writing it directly to memory. Sometime later this data is independently written to memory, as shown in Figure 4-4.
Figure 4-4 Write Back Protocol
Write back from the primary data cache goes to the secondary cache, and write back from the secondary cache goes to main memory, through the system interface. The primary data cache is written back to the secondary cache before the secondary cache is written back to the system interface.
The data cache is indexed with a virtual address and tagged with a physical address. Each primary cache block is in one of the following four states:
A primary data cache block is said to be Inconsistent when the data in the primary cache has been modified from the corresponding data in the secondary cache. The primary data cache is maintained as a subset of the secondary cache where the state of a block in the primary data cache always matches the state of the corresponding block in the secondary cache.
A data cache block can be changed from one state to another as a result of any one of the following events:
These events are illustrated in Figure 4-5, which shows the primary data cache state diagram.
Figure 4-5 Primary Data Cache State Diagram
Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96
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